1. Field of the Invention
The present invention generally relates to multiple sequential lithography processes and, more particularly, to metrology techniques for measurement and characterization of overlay and alignment accuracy for sequential lithographic exposures and in-line and on-line lithographic exposure, scanner or stepper tools.
2. Description of the Prior Art
Lithography processes are currently used in many research and manufacturing environments. Among these environments, one of the more economically important is that of semiconductor integrated circuit manufacture. In this field, increased functionality, performance and potential economy of manufacture has driven the development of numerous successive generations of devices having minimum feature size regimes of increasingly small dimensions and correspondingly increased device density. Currently, feature size regimes of one-quarter micron are available in commercial devices with significant further reductions of minimum feature size foreseeable or in experimental stages of development.
While sophisticated processes have been developed allowing production of structures much smaller than can be resolved by known lithographic processes, it can be understood that at least one lithographic process is required to establish the location and basic dimensions of various electronic devices (e.g. transistors, capacitors and the like) on the wafer and chip areas thereof. However, as a practical matter, numerous lithographic exposures and processes are generally required since formation of devices in different areas and different layers are generally included in current and foreseeable designs.
For example, at extremely small minimum feature size regimes, if different structures of a particular device, such as the gate and channel of a field-effect transistor must be formed with different lithographic processes, overlay accuracy must be maintained at a high level to avoid significantly altering electrical characteristics of the device. In much the same manner, interlayer connections (e.g. vias, studs and interconnect layer patterns) must be overlaid on each other with extreme accuracy in order to reliably and repeatably form low resistance connections which will remain reliable when placed in service. The accuracy of positioning in all of these circumstances will hereinafter be referred to as overlay accuracy.
It has been observed that integration density in successive generations of integrated circuits roughly doubles every two to three years. This increase in integration density corresponds to a reduction of minimum feature size of about 30% over similar periods. The overlay accuracy requirement must be held to a fraction (generally about one-third or less) of the minimum feature size to maintain device geometry and connection reliability. To maintain such accuracy, overlay and stitching measurement accuracy (mean value plus or minus 3 sigma) must be maintained to a metrology error budget of about 10% or less of the maximum allowable overlay error or about 3% of the minimum feature size (less than 6 nm for 0.18 micron minimum feature size technology).
Commonly used metrology techniques are based upon optical microscopy observation of overlay targets for quantifying the overlay error. These techniques have relied upon a feature-in-feature imaging process where a feature such as a square or line is formed within another generally similar shape (e.g., box-in-box or line-in-line) to define the overlay target. The smallest feature size of the overlay target is typically of the order of 1 micron, so that it can be imaged with high contrast, well within the resolution limit of a conventional optical microscope.
Measurement of these overlaid features with, for example, a scanning electron microscope (SEM) of atomic force microscope (AFM) has allowed measurement data to be developed which can be processed to provide measurement resolution somewhat greater than the resolution of available lithography tools, even though the features measured are typically larger than the features which can be lithographically resolved. However, such measurement techniques require complex and expensive SEM or AFM tools which are inherently of low throughput and the measurement is necessarily destructive, decreasing manufacturing yield.
Perhaps more importantly, decreases in minimum feature size and increases in integration density have required increasingly complex, expensive and difficult to use measurement tools while measurements produced are of reduced repeatability, reproducibility, tool induced shift (which are the principal components of the metrology error budget) and quantitative certainty (e.g. confidence factor) as limits of both lithographic and microscopic resolutions are approached, particularly when the imaged features measured are necessarily much larger than the minimum feature size. Further, it is not only necessary to quantitatively evaluate the positioning accuracy of overlaid or stitched together features, but the profile of the exposed and developed resist and/or lithographically produced structures must also be evaluated in separate measurements in order to assure that structures with the desired electrical properties are produced.
Thus, it is seen that, at the present state of the art, known overlay measurement techniques can only be extended to smaller regimes of feature size at relatively great tool expense and process difficulty and complexity and increasing uncertainty and decreasing repeatability of result. Further, it is not at all clear that advances in microscopy processes or other inspection devices which rely upon imaging of features will be able to support manufacturing processes of foreseeable regimes of integrated circuit feature size and integration density.
Spectroscopic reflectometry and spectroscopic ellipsometry are known and well-understood techniques for making quantitative observations of surfaces and structures but have only rarely been applied to lithographic processes or characterization of the performance of lithography tools. However, one such application is the use of specular scatterometry to provide a non-destructive measurement of profiles of resist grating patterns of high resolution. This was presented by Spanos and his students (X. Niu, N. Jakatdar) at the First Small Feature Reproducibility workshop (UC SMART Program Review, of which the assignee of the present invention is a funding participant), held at the University of California on Nov. 18, 1998. Spanos outlined plans to use a spectroscopic ellipsometry sensor to extract profiles of 180 nm and 150 nm linewidth resist features. FIG. 8, derived from that presentation shows spectral response curves of Log(Tan Ψ), the amplitude ratio of complex 0th order TE and TM reflectivities, for two sets of nominal linewidth features (250 nm and 100 nm) with ±7% variation linewidths. The result for the 100 nm feature shows a ±7% linewidth variation on a 100 nm nominal feature (or 7 nm) produces differing spectral curves that can be used to measure linewidth. However, it should be recognized that the curves are quite similar in shape since they are produced by regularly spaced features, and that both the shape of the spectral curves and the location of the various peaks and valleys can be used to evaluate the linewidth corresponding to a measured spectral curve, by best fit comparison to a library of spectral curves, previously generated by simulation and verified by comparison to calibration experimental data.
Specular spectroscopic ellipsometry measures the 0th order diffraction responses of a grating at multiple wavelengths and fixed incidence angle using a spectroscopic ellipsometer sensor. A description of the measurement technique can be found in the publication “Specular Spectroscopic Scatterometry in DUV Lithography” by X. Niu et al. (SPIE, Vol. 3677, pp. 159-168, March, 1999. The ellipsometer sensor measures complex reflectivity for two orthogonal light polarizations.